PIC16F873T-04E/SO【PDF 200/218 页】IC MCU FLASH 4KX14 EE 28SOIC

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Sheet目录3889

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PIC16F87X

DS30292C-page 80

2001 Microchip Technology Inc.

FIGURE 9-11:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

9.2.9

I2C MASTER MODE START

CONDITION TIMING

To initiate a START condition, the user sets the START

condition enable bit, SEN (SSPCON2<0>). If the SDA

and SCL pins are sampled high, the baud rate genera-

tor is reloaded with the contents of SSPADD<6:0> and

starts its count. If SCL and SDA are both sampled high

when the baud rate generator times out (TBRG), the

SDA pin is driven low. The action of the SDA being

driven low while SCL is high is the START condition,

and causes the S bit (SSPSTAT<3>) to be set. Follow-

ing this, the baud rate generator is reloaded with the

contents of SSPADD<6:0> and resumes its count.

When the baud rate generator times out (TBRG), the

SEN bit (SSPCON2<0>) will be automatically cleared

by hardware. The baud rate generator is suspended,

leaving the SDA line held low, and the START condition

is complete.

9.2.9.1

WCOL Status Flag

If the user writes the SSPBUF when a START

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 9-12:

FIRST START BIT TIMING

SDA

SCL

SCL de-asserted but slave holds

DX-1

BRG

SCL is sampled high, reload takes

place, and BRG starts its count

03h

02h

01h

00h (hold off)

03h

02h

Reload

BRG

Value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements

(on Q2 and Q4 cycles)

Note:

If, at the beginning of START condition, the

SDA and SCL pins are already sampled

low, or if during the START condition the

SCL line is sampled low before the SDA

line is driven low, a bus collision occurs,

the Bus Collision Interrupt Flag (BCLIF) is

set, the START condition is aborted, and

the I2C module is reset into its IDLE state.

Note:

Because

queueing

events

not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the START

condition is complete.

SDA

SCL

TBRG

1st Bit

2nd Bit

TBRG

SDA = 1,

At completion of START bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

Hardware clears SEN bit

TBRG

Write to SEN bit occurs here

Set S bit (SSPSTAT<3>)

and sets SSPIF bit

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